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![[Layout of core memory]](core-layout.gif)
The toroids of core memory are organized in such a way that all the bits of a machine word can be accessed in parallel. A machine word is defined as the smallest addressable unit of computer memory. However, modern computers usually address memory in units of bytes. One byte has a size of eight bits. The diagram D2 shows the cores used to store the bits of one byte. To address these bits one X-driver line and eight Y-driver lines have to be activated. The activated lines are rendered in red color.
Driving the proper X-driver and Y-driver lines for reading or writing a specific byte or machine word is the task of the address decoder. The address decoder takes an address of a numeric form and maps it to the corresponding rows and columns of the core plane. On a plane consisting of multiple matrixes, it has to select the proper matrix as well. The decoder logic is quite complex, so it was frequently placed on a separate board.
![[M8148 memory controller]](m8148-small.jpg)
[Larger image 640x350, 48K bytes]
The picture shows a DEC M8148 core memory controller and timing module. It contains the address decoder, the UNIBUS mapping logic, and the timing components used to generate the pulses for reading and writing the core memory.
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Nils M Holm 2004, 2008
